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R1EX25002Axx00A/R1EX25004Axx00A
Data Protect
The Block Protect bits (BP1, BP0) define the area of memory that is protected against the execution of write cycle, as
summarized in the following table.
When Write Protect ( W ) is driven low, write to memory array (WRITE) and write status register (WRSR) are disabled,
and WEL bit is reset.
Write Protected Block Size
Status register bits
Array addresses protected
0
0
1
1
BP1
0
1
0
1
BP0
Protected blocks
None
Upper quarter
Upper half
Whole memory
R1EX25004A
None
180h ? 1FFh
100h ? 1FFh
000h ? 1FFh
R1EX25002A
None
C0h ? FFh
80h ? FFh
00h ? FFh
Hold Condition
The hold ( HOLD ) signal is used to pause any serial communications with the device without resetting the clocking
sequence.
During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C)
are don’t care.
To enter the hold condition, the device must be selected, with chip select ( S ) low.
Normally, the device is kept selected, for the whole duration of the hold condition. Deselecting the device while it is in
the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to
reset any processes that had been in progress.
The hold condition starts when the hold ( HOLD ) signal is driven low at the same time as serial clock (C) already being
low (as shown in the following figure).
The hold condition ends when the hold ( HOLD ) signal is driven high at the same time as serial clock (C) already being
low.
The following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock
(C) being low.
Hold Condition Activation
HOLD status
C
HOLD
REJ03C0357-0002 Rev. 0.02 Jan.14 .2009
page 17 of 20
HOLD status
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